In recent years, heterojunction bipolar transistors (HBTs) array with parallel HBT cells layout has been used widely for microwave power applications^[1–4] due to its high current handling capability.^[5–7] However, the self-heating effect caused by the power dissipation of each HBT cell and the thermal coupling effect among the adjacent HBT cells result in an uneven temperature profile in the HBTs array. Because of the positive temperature coefficient of the emitter current, the central HBT cells with higher temperature will conduct more current and consequently generate more heat, which aggravates the thermal effects and leads to thermal breakdown or thermal runaway.^[8,9]

In order to obtain more uniform temperature distribution and tackle these thermal issues, one-dimensional (along emitter width direction) layout design technologies including variation of emitter length in HBT cells^[10,11] (in Fig. 1(a)) and variation of emitter spacing between HBT cells^[12–15] (in Fig. 1(b)) are used widely, which could decrease the temperature difference along the emitter width direction. However, there is still a higher temperature in the center of each emitter. At the same time, the non-uniformity of the temperature profile along the emitter length direction is not reduced. In recent research, the technology of multi-emitter array (in Fig. 1(c)) is proposed to decrease the temperature difference along the emitter length direction effectively,^[16,17] which shows the superior thermal properties of the HBTs array with two-dimensional parallel HBT cells layout (2-D HBTs array). However, the layout design methodology of 2-D HBTs array has not been studied.

Fig. 1.

	Figure Option ViewDownloadNew Window
	Fig. 1. Three-dimensional schematic structures of HBTs arrays with different layout designs: (a) variation of emitter length in one-dimensional layout design (M HBT cells), (b) variation of emitter spacing in one-dimensional layout design (M HBT cells), (c) two-dimensional parallel layout design (N × M HBT cells).

It is known that the thermal resistance matrix ([R_ij]) could be used to represent the thermal effects of a one-dimensional HBT array,^[18,19] which is helpful to design the layout of the device. However, the prior [R_ij] representation is not applicable for the 2-D HBTs array.

In this paper, with the aid of the thermal network of a 2-D HBTs array, a new thermal resistance matrix ([R_ijkl]) is proposed, including self-heating thermal resistance (R_ijij) in the (i, j) HBT cell and thermal coupling resistance ( to represent the self-heating and thermal coupling effects, respectively. The dependence of [R_ijkl] on cell spacing along the emitter length direction (S_x) and cell spacing along the emitter width direction (S_y) is also studied respectively. Furthermore, with the aid of [R_ijkl], the HBTs array with a novel 2-D non-uniform cell spacing layout (including non-uniform S_x and non-uniform is designed to lower the peak junction temperature, reduce the non-uniformity of the temperature profile, and hence alleviate the thermal issues of the HBTs array.

To account for the self-heating and the thermal coupling effects, a thermal network of 2-D HBTs array (N × M HBT cells) with a ground-referenced thermal voltage is shown in Fig. 2, where each HBT cell is assigned with a constant temperature (e.g., its average temperature).

Fig. 2.

	Figure Option ViewDownloadNew Window
	Fig. 2. Thermal network of a two-dimensional HBTs array with N × M HBT cells by taking into account the self-heating and thermal coupling effects.

For the (i, j) HBT cell in the thermal network, the self-heating effect can be represented as a parallel combination of R_ijij and dissipated power (P_ij). The self-heating temperature rise of the (i, j) HBT cell ( ) is obtained as . Meanwhile, the thermal coupling effect can be represented as a series thermal coupling voltage, which is a combination of the temperature rise caused by the rest HBT cells. The thermal coupling temperature rise of the (i, j) HBT cell ( ) is obtained as

Therefore, the peak junction temperature of the (i, j) HBT cell (T_ij) including the self-heating temperature rise and the total thermal coupling temperature rise is obtained as

As a result, the thermal-electrical model is established based on the iterative solution between ANSYS and MATLAB, and the temperature of the HBTs array (with N × M HBT cells) is first calculated under the same power level. By increasing the power of the (k, l) HBT cell ( ), a new temperature distribution is calculated. Therefore, [R_ijkl] including R_ijij and is obtained by using the temperature rise of the (i, j) HBT cell ( ) as

2.1. Impact of cell spacing along emitter length direction

Take a 2 × 1 HBTs array for example, [R_ijkl] is calculated, and the impact of cell spacing along the emitter length direction (S_x) on the thermal characteristics of the HBTs array is studied. The layout of the 2 × 1 HBTs array is shown in Fig. 3, where both the chip width (W) and the chip length (L) is , the width (w) and the length (l) of each HBT cell is and , respectively.

Fig. 3.

	Figure Option ViewDownloadNew Window
	Fig. 3. The layout of a 2 × 1 HBTs array.

The impact of S_x on R_ijij and is shown in Figs. 4 and 5, respectively. It can be seen that R_ijij decreases as S_x increases from to due to the increase of the heat dissipation path. However, R_ijij increases exponentially when S_x increases beyond . It is because both the front-edge and back-edge surfaces of the chip along the emitter length direction are adiabatic, which restrict the lateral spread of the heat flow spread from the heat source to the outside. Different from R_ijij, keeps decreasing as S_x increases, and the trend of can be approximated by an exponential function, indicating that the effective thermal coupling exists when two cells are very close to each other.

Fig. 4.

	Figure Option ViewDownloadNew Window
	Fig. 4. The self-heating thermal resistance versus cell spacing along emitter length direction in the 2 × 1 HBTs array.

Fig. 5.

	Figure Option ViewDownloadNew Window
	Fig. 5. The thermal coupling resistance versus cell spacing along emitter length direction in the 2 × 1 HBTs array.

The impact of S_x on the peak junction temperature (T_ij) at I_C of 0.4 mA and V_CE of 5 V is shown in Fig. 6, where the trend of T_ij is almost the same as that of R_ijij. It is because is far less than R_ijij in the [R_ijkl] of the given 2 × 1 HBTs array and the trend of T_ij is mainly determined by R_ijij.

Fig. 6.

	Figure Option ViewDownloadNew Window
	Fig. 6. The peak junction temperature versus cell spacing along emitter length direction in the 2 × 1 HBTs array.

2.2. Impact of cell spacing along emitter width direction

Take a 1 × 2 HBTs array for example, [R_ijkl] is calculated, and the impact of cell spacing along the emitter width direction (S_y) on the thermal characteristics of the HBTs array is studied. The layout of the 1 × 2 HBTs array is shown in Fig. 7, where both the chip size and the size of each HBT cell is the same as those of the 2 × 1 HBTs array. S_y is the cell spacing along the emitter width direction.

Fig. 7.

	Figure Option ViewDownloadNew Window
	Fig. 7. The layout of a 1 × 2 HBTs array.

The impact of S_y on R_ijij and is shown in Figs. 8 and 9, respectively. It can be seen that R_ijij decreases linearly as S_y increases from to , and increases exponentially when S_y increases beyond . It is because the lateral spread of heat flow is restricted by the left and right edges of the chip and the spreading angle of the heat flow is decreased, which decrease the heat dissipation path and lead to the increase of R_ijij. At the same time, keeps decreasing exponentially as S_y increases.

Fig. 8.

	Figure Option ViewDownloadNew Window
	Fig. 8. The self-heating thermal resistance versus cell spacing along emitter width direction in the 1 × 2 HBTs array.

Fig. 9.

	Figure Option ViewDownloadNew Window
	Fig. 9. The thermal coupling resistance versus cell spacing along emitter width direction in the 1 × 2 HBTs array.

Figure 10 shows the impact of S_y on T_ij at I_C of 0.4 mA and V_CE of 5 V, where T_ij decreases with a parabola distribution as S_y increases from to , and remains approximately constant when S_y increases beyond . It is because is in the same order with R_ijij, and hence both and R_ijij will affect the thermal characteristics of the HBTs array.

Fig. 10.

	Figure Option ViewDownloadNew Window
	Fig. 10. The peak junction temperature versus cell spacing along emitter width direction in the 1 × 2 HBTs array.

From this analysis, it can be concluded that both S_x and S_y should be designed carefully to effectively decrease R_ijij and . The decrease of R_ijij and is helpful for lowering the peak junction temperature of HBTs array, which sheds light on adopting a 2-D non-uniform cell spacing layout to improve the thermal characteristics of HBTs array.

Take a HBTs array with 1 × 20 HBT cells for example, both the simulated temperature profile along the central line across the HBT cells and the measured temperature profile reported in Ref. [15] are shown in Fig. 11. The simulated temperature profile matches well with the measured data, verifying the thermal-electrical model used in the simulations.

Fig. 11.

	Figure Option ViewDownloadNew Window
	Fig. 11. Comparison of measured and simulated temperature profiles of a HBTs array with 1 × 20 HBT cells at A and .

With the aid of the thermal-electrical model, [R_ijkl] of a 2 × 6 HBTs array (array-1) with uniform cell spacings of along the emitter length direction and along the emitter width direction is calculated at I_C of 2.4 mA and V_CE of 5 V

The detail profile of [R_ijkl] in array-1 is shown in Fig. 12.

Fig. 12.

	Figure Option ViewDownloadNew Window
	Fig. 12. Profile of thermal resistance matrix [Rijkl] (K/W) in the 2 × 6 HBTs array with uniform cell spacing (array-1) at IC of 2.4 mA and VCE of 5 V.

At the same time, iterations are used to calculate T_ij and P_kl of array-1. First, it is assumed that there is an even collector current distribution across all HBT cells. Due to the thermal effects, the temperature of each HBT cell can be calculated with a temperature rise different from the others’. Because of the positive temperature coefficient of in Eq. (5), the collector current ( ) as well as the dissipated power (P_kl) of each HBT cell is redistributed and leads to a new distribution of T_ij. The above steps are iterated until the final steady-state solutions are achieved. The steady-state results of P_kl in array-1 are shown in Fig. 13. The temperature profile of array-1 is shown in Fig. 14.

Fig. 13.

	Figure Option ViewDownloadNew Window
	Fig. 13. The distribution of the dissipated power (Pkl) in the 2 × 6 HBTs array with uniform cell spacing (array-1) at IC of 2.4 mA and VCE of 5 V.

Fig. 14.

	Figure Option ViewDownloadNew Window
	Fig. 14. Temperature profile of the 2 × 6 HBTs array with uniform cell spacing (array-1) at IC of 2.4 mA and VCE of 5 V.

In order to improve the uniformity of the P_kl distribution and lower the temperature of the central HBT cells, both of cell spacing along the emitter length direction (S_x) and cell spacing along the emitter width direction (S_y) are designed carefully. For S_x, the spacings between the central cells should be increased significantly to lower R_ijij, because is far less than R_ijij for the cells along the emitter length direction and the temperature difference is mainly determined by R_ijij. For the spacings between the central cells are increased moderately to lower both R_ijij and . It is because is in the same order with R_ijij for the cells along the emitter width direction and the temperature difference is determined by both R_ijij and . Moreover, the temperature difference will remain approximately constant as S_y increase to a certain distance. At the same time, considering that the outside cells are more convenient to spread heat, both S_x and S_y of the outside cells can be decreased to keep the total cell spacing unchanged. A 2 × 6 HBTs array (array-2) with non-uniform S_x and non-uniform S_y is designed under the same power density of array-1. The detail values of S_x and S_y of the two types of HBTs arrays are presented in Tables 1 and 2, respectively. The layouts of the two types of HBTs arrays are also presented in Fig. 15. Array-2 also has an identical vertical structure, total emitter area, and total cell spacing to those of array-1. The detail profile of [R_ijkl] in array-2 is shown in Fig. 16. For array-2, not only R_ijij of each HBT cell but also in the central HBT cells decrease obviously, when compared with those of array-1. Take the central (1, 3) HBT cell for example, of the two types of HBTs arrays is respectively given by

Fig. 15.

	Figure Option ViewDownloadNew Window
	Fig. 15. Layouts of 2 × 6 HBTs arrays (a) with uniform Sx and uniform Sy (array-1), (b) with non-uniform Sx and non-uniform Sy (array-2).

Fig. 16.

	Figure Option ViewDownloadNew Window
	Fig. 16. Profile of thermal resistance matrix [Rijkl] (K/W) in the 2 × 6 HBTs array with non-uniform Sx and non-uniform Sy (array-2) at IC of 2.4 mA and VCE of 5 V.

Table 1.

Table 1.

Table 1. Cell spacing along emitter length direction of the two types of HBTs arrays. . Array-1 0.25 0.25 0.25 0.25 0.25 0.25 Array-2 0.1 0.25 0.4 0.4 0.25 0.1

Table 1. Cell spacing along emitter length direction of the two types of HBTs arrays. .

Table 2.

Table 2.

Table 2. Cell spacing along emitter width direction of the two types of HBTs arrays. . Array-1 1.3 1.3 1.3 1.3 1.3 Array-2 1.1 1.3 1.7 1.3 1.1

Table 2. Cell spacing along emitter width direction of the two types of HBTs arrays. .

The correlated P_kl and the temperature profile of array-2 are shown in Figs. 17 and 18, respectively. For array-2, the maximum power level difference of the HBT cells is decreased by 38.7% when compared with that of array-1. As a result, array-2 has a lower peak junction temperature of 407.7 K, which is lowered by 4.2% and the uniformity of the cell temperature is improved by 46.9%.

Fig. 17.

	Figure Option ViewDownloadNew Window
	Fig. 17. The distribution of the dissipated power (Pkl) in the 2 × 6 HBTs array with non-uniform cell spacing (array-2) at IC of 2.4 mA and VCE of 5 V.

Fig. 18.

	Figure Option ViewDownloadNew Window
	Fig. 18. Temperature profile of the 2 × 6 HBTs array with non-uniform cell spacing (array-2) at IC of 2.4 mA and VCE of 5 V.

As the collector–emitter voltage V_CE is increased to 7 V, the calculated correlated P_kl and T_ij of the HBT cells in the two arrays are shown in Figs. 19 and 20, respectively. For array-2, the maximum power level difference is decreased by 36.5%, the peak junction temperature is lowered by 20.2 K, and the uniformity of the cell temperature is improved by 52.7%, when compared with those of array-1. It indicates that, for the HBTs array with designed non-uniform cell spacing, the high power-handling capability and thermal dissipation capability are kept when V_CE increases.

Fig. 19.

	Figure Option ViewDownloadNew Window
	Fig. 19. Power levels at for HBTs array with uniform cell spacing (array-1) and HBTs array with varying cell spacing (array-2).

Fig. 20.

	Figure Option ViewDownloadNew Window
	Fig. 20. The peak junction temperature profiles at heat source surface of HBTs array with uniform cell spacing (array-1) and HBTs array with varying cell spacing (array-2) at .

To represent the self-heating effect and thermal coupling effect of the HBTs array with N × M HBT cells, [R_ijkl] including R_ijij and is presented in this paper. With the aid of a thermal network, the thermal-electrical model is established based on the iterative solution between ANSYS and MATLAB, and [R_ijkl] of the HBTs array are calculated. The dependence of [R_ijkl] and peak junction temperature T_ij on cell spacing (S_x and S_y) is also investigated. For HBT cells along the emitter length direction, T_ij decreases as S_x increases from to , and T_ij increases exponentially when S_x increases beyond . The trend of T_ij versus S_x is mainly determined by the variation of R_ijij. However, for HBT cells along the emitter width direction, T_ij decreases as S_y increases from to , and T_ij remains approximately constant when S_y increases beyond , where the trend of T_ij versus S_y is determined by both R_ijij and . As a result, the moderate increase of S_x and S_y could effectively lower R_ijij and as well as T_ij. Furthermore, by taking a 2 × 6 HBTs array for example, the 2-D non-uniform cell spacing layout (including non-uniform S_x and non-uniform is designed. For the optimized HBTs array, the peak junction temperature is lowered by 4.2%, the uniformity of the cell temperature is improved by 46.9%, and the maximum power level difference of the HBT cells is decreased by 38.7%, when compared with those of the uniform device. At the same time, the high power-handling capability and thermal dissipation capability are kept as V_CE increases from 5 V to 7 V, indicating that the 2-D non-uniform cell spacing layout is a useful method to design power HBTs arrays for high thermal stability.